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Advanced VHDL for Design
Description

Corso di 3 giorni orientato all'uso di tecniche e costrutti del VHDL non comunemente usati.

DURATION
3 giorni
TARGET AUDIENCE
Progettisti e verification engineers che usano il VHDL per lo sviluppo dei progetti desiderosi di migliorare ed incrementare le conoscenze per l'uso di tecniche di programmazione avanzate.
PREREQUISITES
Conoscere il VHDL ed avere esperienza nella progettazione di dispositivi con tale linguaggio.
ARGUMENTS COVERED
  • Introduction
    • Recap of design units
    • Latest VHDL Standards
    • The RTL Synthesis Subset
    • Books and Other Resources
  • The ASIC Design Flow
    • VHDL in the Design Flow
    • Effects of Coding on Synthesis Results
    • Coding Styles and Synthesis Runtime
  • Type Guidelines
    • Types and Subtypes
    • Recommended Types for Synthesis
  • Preparing for Reuse
    • Advantages of Reuse
    • Designing Reusable IP
  • Managing VHDL Libraries
    • Limitations of Standard Approaches
    • Recommended Library Structure
  • Exploiting Entities and Architectures
    • Types of Design Unit
    • Advantages of Multiple Architectures
    • Synthesis Considerations
  • Using Sub-programs Efficiently
    • Sub-program recap
    • Reasons for Using Sub-programs
    • Synthesis Limitations
  • VHDL Configurations
    • The Power of Configurations
    • What Works With Synthesis
  • Optimising for Power
    • Power Reduction Techniques
    • RTL Tips to Reduce Power
  • Optimising for Speed
    • Techniques to Improve Design Performance
    • RTL Tips to Improve Performance
  • Optimising for Area
    • Techniques to Reduce Area
    • RTL Tips to Reduce Area
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