System Verilog for Verification
Description
Corso di 4 giorni rivolto a chi gia' si occupa della verifica di dispositivi integrati digitali e vuole passare alla verifica tramite l'uso del SystemVerilog.
DURATION
4 giorni
TARGET AUDIENCE
Verification engineers che vogliono imparare ed usare le tecniche di verifica avanzate fornite dal System Verilog.
PREREQUISITES
Conoscenza del Verilog
ARGUMENTS COVERED
- Introduction to Verification with SystemVerilog
- Language enhancements
- SystemVerilog Data types
- Arrays & Structures
- SV Scheduler
- Program Control
- Hierarchy
- Tasks & Functions
- Dynamic Processes
- Interprocess Sync & Communication
- Classes
- Class basics
- Constructors
- Virtual Interfaces
- Inheritance
- Parameterization
- Polymorphism
- Randomization & Constraints
- Randomize
- Constraints
- Random sequences
- Functional Coverage
- Covergroups
- Coverpoints and cross
- System Verilog Assertions
- Immediate assertions
- Concurrent assertions basics
- Boolean expressions
- Sequences
- Property block
- Verification directives
- Sequence blocks
- Sequence operators, methods & expressions
- Property operators & expressions
- Data use
- Verification directives
- Multiple clocks